diff --git a/board/mpc8641hpcn/init.S b/board/mpc8641hpcn/init.S
index 5f19fdf..69954a8 100644
--- a/board/mpc8641hpcn/init.S
+++ b/board/mpc8641hpcn/init.S
@@ -1,6 +1,6 @@
 /*
  * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown (jeffrey@freescale.com)
+ * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -59,7 +59,6 @@
 #define LAWAR2	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
 
 #define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
-/*#define LAWAR3	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) */
 #define LAWAR3	(~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
 
 /*
@@ -72,7 +71,6 @@
 #define LAWAR5	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
 
 #define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
-/*#define LAWAR6	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) */
 #define LAWAR6	(~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
 
 #define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
@@ -86,7 +84,7 @@
 #define LAWAR8  ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
 #endif
 
-      	.section .bootpg, "ax"
+	.section .bootpg, "ax"
 	.globl	law_entry
 law_entry:
 	lis	r7,CFG_CCSRBAR@h
@@ -110,8 +108,8 @@
 	stwu    r6, 0x20(r4)
 
 	lis     r6,LAWAR2@h
-        ori     r6,r6,LAWAR2@l
-        stwu    r6, 0x20(r5)
+	ori     r6,r6,LAWAR2@l
+	stwu    r6, 0x20(r5)
 
 	/* LAWBAR3, LAWAR3 */
 	lis     r6,LAWBAR3@h
@@ -127,7 +125,7 @@
 	ori     r6,r6,LAWBAR4@l
 	stwu    r6, 0x20(r4)
 
-        lis     r6,LAWAR4@h
+	lis     r6,LAWAR4@h
 	ori     r6,r6,LAWAR4@l
 	stwu    r6, 0x20(r5)
 	/* LAWBAR5, LAWAR5 */
@@ -157,14 +155,14 @@
 	ori     r6,r6,LAWAR7@l
 	stwu    r6, 0x20(r5)
 
-       /* LAWBAR8, LAWAR8 */
-       lis     r6,LAWBAR8@h
-       ori     r6,r6,LAWBAR8@l
-       stwu    r6, 0x20(r4)
+	/* LAWBAR8, LAWAR8 */
+	lis     r6,LAWBAR8@h
+	ori     r6,r6,LAWBAR8@l
+	stwu    r6, 0x20(r4)
 
-       lis     r6,LAWAR8@h
-       ori     r6,r6,LAWAR8@l
-       stwu    r6, 0x20(r5)
+	lis     r6,LAWAR8@h
+	ori     r6,r6,LAWAR8@l
+	stwu    r6, 0x20(r5)
 
 	blr